Vector Modulator for 5G Transceivers in 65 nm CMOS

Abstract

This paper presents simulation results of an inductorless vector modulator in a standard 65 nm CMOS technology. The designed modulator is based on a vector-sum phase shifter and for five bit amplitude resolution and six bit phase resolution demonstrates 0.2 dB and 1.0 deg. RMS amplitude and RMS phase error in 4-6 GHz band. Input CP1dB is about –7.8 dBm with power consumption of 31 mW and maximum gain of 1.9 dB at 4.9 GHz.