Synthesis of control unit with refined state encoding for CPLD devices

Abstract

The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.