LVDCSL: low voltage differential current switch logic, a robust low power DCSL family

Abstract

In this paper we present a robust Differential Current Switch Logic gate suitable for low V/sub DD/, low power operation. Differential Current Switch Logic gates achieve high performance and low power by restricting internal node voltage swings. Traditional DCSL is, however, highly sensitive to load imbalance because of the presence of a cross coupled inverter pair at the output. In this paper we describe LVDCSL, a low voltage DCSL family which preserves the essential features of DCSL namely, high speed, low power, restricted internal voltage swings and a latching input stage. However, it is much more robust to mismatched output loads, and is capable of working at far lower voltages. In addition spikes in output transitions are greatly reduced simplifying interface to conventional CMOS circuits. Our results show that LVDCSL is capable of working at under 2 volts in a 0.35 /spl mu/m CMOS process while being faster than comparable Domino gates. At the same time total power consumption is reduced. LVDCSL achieves 40% delay improvement and 22% power reduction in comparison with Domino gates.