Design and Performance Analysis of Voltage-Controlled Oscillator

Abstract

In this paper, a 3-stage PG-ring VCO is designed using a power gating technique in cadence virtuoso and 180nm technology. Here, the efficiency of a 3-stage PG-ring VCO is evaluated by comparing its performance to that of other VCOs. Power gating techniques are utilized to reduce circuit leakage. The analysis is conducted using various design techniques and transistor sizes. It has been observed that a 3-stage PG-ring oscillator offers better performance in terms of various metrics, including power, frequency, energy, and power delay transistor count product (PDNP), with transistor dimensions.