Malware Identification in Advanced Interconnects on SOC

Abstract

The main objective is to simulate Advanced interconnects used to connect System on Chip and identification of Malware present in the interconnects. The changed device-style incorporating test bench as a master driver is used. The versatile interconnect design is used for various types of bus transfers. Data bounding a secure transmission was achieved, as specified. The usage of verification module as a master will decrease the size of the circuit. The Malware inside the hardware is noticed whenever it was set off. This paper describes malware detection in Advanced- Micro-Controller- Bus-Architecture (AMBA) Advanced High-performance Bus (AHB) implementation is carried out by Verilog coding. In read/write operation the malware was implemented by simulator of Xilinx.