ATPG of Digital Electronic Systems BIST Based on D-PL Chaotic Model

Abstract

A D-PL ( Digital-PL) chaotic model was proposed to construct ATPG (Automatic Test Pattern Generation) of BIST (Built in Self Test) in this paper. The D-PL chaotic model is improvement of the traditional continuous PL chaotic model. The coefficient of power of 2 was used for traditional PL chaos discrete processing. This approach is conducive to the realization of hardware. Shift registers and accumulator adopted to implement iteration avoiding the direct use of the multiplier. This method can effectively reduce the circuits area After parameters optimization, the D-PL chaotic model ATPG was applied for testing digital circuits. Experiment results show that the proposed D-PL chaotic model ATPG has good randomness and ergodicity. The test pattern of D-PL Model has no correlation. It can effectively improve the digital circuits fault detection rate in BIST.