Assertion Based Verification using Yosys: A Case Study from Nuclear Domain

Shubam Gupta, Ajith K. John, M. Kalra
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Abstract

Assertion Based Verification is a design methodology that integrates Formal Methods as part of the design process. As each module is designed, the designer expresses the functional, structural and interface requirements of the module as logical formulas called assertions. These assertions are then verified using simulation and/or formal verification. This paper aims at studying the effectiveness of applying formal verification during Assertion Based Verification in the development of VHDL design for a VME-bus for safety applications in nuclear reactors. Assertions for the VHDL modules developed were expressed in PSL, and were proved using three industrially successful and popular formal verification algorithms – Bounded Model Checking, K-Induction, and Property Driven Reachability, implemented in an open-source verification tool, Yosys. Our experiments revealed that Property Driven Reachability completely outperforms K-Induction in all the cases. Bounded Model Checking for a few hundred clock cycles helped us in finding a number of important, but subtle bugs, which were missed by traditional simulation, at the cost of a justifiable increase in design effort towards writing assertions.
使用Yosys进行基于断言的验证:来自核领域的案例研究
基于断言的验证是一种设计方法,它将形式化方法集成为设计过程的一部分。在设计每个模块时,设计人员将模块的功能、结构和接口需求表示为称为断言的逻辑公式。然后使用模拟和/或正式验证来验证这些断言。本文旨在研究在核反应堆安全应用vme总线的VHDL设计开发中,在基于断言的验证过程中应用形式化验证的有效性。开发的VHDL模块的断言用PSL表示,并使用三种工业上成功且流行的形式验证算法进行了证明——有界模型检查、k -归纳和属性驱动可达性,这些算法在开源验证工具Yosys中实现。我们的实验表明,属性驱动的可达性在所有情况下都完全优于k -归纳。对几百个时钟周期的有限模型检查帮助我们发现了许多重要但微妙的错误,这些错误被传统的模拟忽略了,其代价是合理地增加了编写断言的设计工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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