Analog integrated circuit design of a hypertrellis decoder

Abstract

The first integrated analog hypertrellis decoder for a nonbinary (5, 4) single check code over Z4 (the integer ring modulo 4) is presented. Computation is performed at 50MHz in cascode current mode for efficient routing, accuracy and speed. Hard decision outputs are generated for efficient testing, while soft outputs are available for accuracy testing. The chip is designed in a 0.5 /spl mu/m Agilent CMOS n-well process and occupies an area of 3.8 mm/sup 2/.