A 10 Gb/s SerDes Transceiver

Abstract

This paper presents a Serial Data Link Transceiver, which supports data rate transfer up to 10 Gbit/s designed with 65-nm CMOS technology. The Transmitter is modeled with Verilog-A with 3-taps Finite Impulse Response Filter (FIR) and Current Mode Logic (CML) drivers. The Receiver is DC-coupled and driven by Power Management Units (PMU), Band Gab Reference (BGR) and Low Drop Out regulator (LDO). The equalization in the receiver is achieved using Continuous Time Linear Equalizer (CTLE) with channel loss compensation up to 7.5 dB, Variable Gain Amplifier (VGA) and programmable 3-taps Decision Feedback Equalizer (DFE). The sampling clock is acquired using Clock and Data Recovery block (CDR). Both the transmitter and the receiver use supply voltage of 1.2V generated from voltage supply of 1.8V using PMU. The receiver average power consumption is 9.57 mW at 10 Gbit/s rate.The Transceiver's equalization is tested over 30-inches of FR4 channel and achieved compensation up to 27 dB loss at the Nyquist frequency (5 GHz).