Investigation of scaling methodology for strained Si n-MOSFETs using a calibrated transport model

Abstract

The performance, calculated in terms of on-current I/sub on/ vs. off-current I/sub off/, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I/sub on/ enhancement for given I/sub off/, but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6/spl times/10/sup 18/ cm/sup -3/, results in reduction of I/sub on/ enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n/sup +/ polysilicon is an attractive approach to achieve the desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents >20% Ge).