A hybrid on-chip network with a low buffer requirement

Abstract

As the CMOS technology develops, the number of buffers required in a network-on-chip increases with flit width. This increase of buffers provides more power and area overhead to a network router. This paper proposes a hybrid packet-switched and circuit-switched network in which the total buffer requirement depends on only the width of the short message and buffer depth, and does not increase with the network width. The performance is maintained through a low latency circuit-switch by using a simple reverse path reservation method. The simulation results indicated that a considerable amount of power and area can be saved by the buffer reduction, whereas performance is maintained.