An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM

Abstract

An embedded 8 b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90 nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100 MHz and consumes 28.4 mW at 1.0 V supply voltage. The embedded RISC enables 100 Mb/s/pin read/write throughputs to PRAM.