Low-cost ladar imagers

Abstract

We have developed low-cost LADAR imagers using photon-counting Geiger avalanche photodiode (GPD) arrays, signal amplification and conditioning interface with integrated active quenching circuits (AQCs) and readout integrated circuit (ROIC) arrays for time to digital conversion (TDC) implemented in FPGA. Our goal is to develop a compact, low-cost LADAR receiver that could be operated with room temperature Si-GPD arrays and cooled InGaAs GPD arrays. We report on architecture selection criteria, integration issues of the GPD, AQC and TDC, gating and programmable features for flexible and low-cost re-configuration, as well as on timing resolution, precision and accuracy of our latest LADAR designs.