Low complexity modified constant Log-Map algorithm for radix-4 turbo decoder

Abstract

Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis VHDL implementation of radix-2 and radix-4 form. In a practical system, the original MAP algorithm is too complex for implementation. All the branch metrics required for calculating LLR values are stored in a RAM. Max* function is implemented with correction factor to improve performance. The proposed, implemented algorithm is almost identical to max* function. With increasing demand for different data rate and services for communication system reconfigurability is important. So implementation is targeted towards Xilinx Virtex E FPGAs. The turbo decoder uses soft in soft out (SISO) decoders to decode one code word.