The Java Virtual Machine in retargetable, high-performance instruction set simulation

M. Kaufmann, Matthias Häsing, Thomas B. Preußer, R. Spallek
{"title":"The Java Virtual Machine in retargetable, high-performance instruction set simulation","authors":"M. Kaufmann, Matthias Häsing, Thomas B. Preußer, R. Spallek","doi":"10.1145/2093157.2093161","DOIUrl":null,"url":null,"abstract":"Two main demands on instruction set simulation are portability and high simulation performance. For the testing and benchmarking of ISA prototypes such as in an ASIP design process, simulators are additionally required to offer retargetability for the rapid modeling and revisal of their simulation targets.\n In this paper, we present the techniques applied in a full-system instruction set simulation framework that combines these three conflicting demands. Our framework is retargetable, portable and provides high simulation performance. It is entirely implemented in Java and features a two-stage dynamic binary translation (DBT) targeting Java Bytecode in the first stage and employing the Java Virtual Machine as an external code generation back end in the second stage. While the use of state-of-the-art techniques such as DBT generates high simulation performance, the framework is also platform independent and can run on any J2SE-compliant Java Runtime Environment. In spite of this platform independence, the native code generated in the second stage will even profit from the platform-specific optimizations performed by modern JVM implementations. Our second contribution is HPADL, the instruction set description language that provides the retargetability of our framework. HPADL is tailored for the specific needs of dynamically compiling full-system IS simulation. Due to its clean separation of concerns between the instruction decoding and instruction execution, it easily enables DBT. Also, it is not restricted to a specific range of target architectures such as RISC. In this paper, we will compare the modeling effort in HPADL to that of QEMU. For our experiments and in order to show the practicability and flexibility of our approach, we implemented HPADL models of the DLX, 8086, ARMv4 and PowerPC/PowerPC VLE ISA as well as some IO device models in Java. A comparison with the simulation performance of QEMU by reference of the EEMBC AutoBench 1.1 shows that we achieve 78% of the QEMU performance on average.","PeriodicalId":169989,"journal":{"name":"Principles and Practice of Programming in Java","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Principles and Practice of Programming in Java","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2093157.2093161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

Two main demands on instruction set simulation are portability and high simulation performance. For the testing and benchmarking of ISA prototypes such as in an ASIP design process, simulators are additionally required to offer retargetability for the rapid modeling and revisal of their simulation targets. In this paper, we present the techniques applied in a full-system instruction set simulation framework that combines these three conflicting demands. Our framework is retargetable, portable and provides high simulation performance. It is entirely implemented in Java and features a two-stage dynamic binary translation (DBT) targeting Java Bytecode in the first stage and employing the Java Virtual Machine as an external code generation back end in the second stage. While the use of state-of-the-art techniques such as DBT generates high simulation performance, the framework is also platform independent and can run on any J2SE-compliant Java Runtime Environment. In spite of this platform independence, the native code generated in the second stage will even profit from the platform-specific optimizations performed by modern JVM implementations. Our second contribution is HPADL, the instruction set description language that provides the retargetability of our framework. HPADL is tailored for the specific needs of dynamically compiling full-system IS simulation. Due to its clean separation of concerns between the instruction decoding and instruction execution, it easily enables DBT. Also, it is not restricted to a specific range of target architectures such as RISC. In this paper, we will compare the modeling effort in HPADL to that of QEMU. For our experiments and in order to show the practicability and flexibility of our approach, we implemented HPADL models of the DLX, 8086, ARMv4 and PowerPC/PowerPC VLE ISA as well as some IO device models in Java. A comparison with the simulation performance of QEMU by reference of the EEMBC AutoBench 1.1 shows that we achieve 78% of the QEMU performance on average.
实现了Java虚拟机中的可重标、高性能指令集仿真
指令集仿真的两个主要要求是可移植性和高仿真性能。对于ISA原型的测试和基准测试,例如在ASIP设计过程中,还需要模拟器提供可重定向性,以便快速建模和修改其仿真目标。在本文中,我们提出了在结合这三个相互冲突的需求的全系统指令集仿真框架中应用的技术。我们的框架是可重定向的,可移植的,并提供高仿真性能。它完全是用Java实现的,在第一阶段以Java字节码为目标,采用两阶段动态二进制转换(DBT),在第二阶段使用Java虚拟机作为外部代码生成后端。虽然使用最先进的技术(如DBT)可以生成高模拟性能,但该框架也是独立于平台的,并且可以在任何符合j2ee的Java运行时环境上运行。尽管有这种平台独立性,但在第二阶段生成的本机代码甚至可以从现代JVM实现执行的特定于平台的优化中获益。我们的第二个贡献是HPADL,这是一种指令集描述语言,它提供了框架的可重定向性。HPADL是为动态编译全系统is仿真的特定需求量身定制的。由于它清晰地分离了指令解码和指令执行之间的关注点,因此很容易实现DBT。此外,它并不局限于特定的目标体系结构范围,例如RISC。在本文中,我们将比较HPADL和QEMU的建模工作。在我们的实验中,为了展示我们方法的实用性和灵活性,我们在Java中实现了DLX、8086、ARMv4和PowerPC/PowerPC VLE ISA的HPADL模型以及一些IO设备模型。通过参考EEMBC AutoBench 1.1与QEMU的仿真性能进行比较,结果表明我们平均达到了QEMU性能的78%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信