The Potential Energy Efficiency of Vector Acceleration

Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norm Jouppi
{"title":"The Potential Energy Efficiency of Vector Acceleration","authors":"Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norm Jouppi","doi":"10.1145/1188455.1188537","DOIUrl":null,"url":null,"abstract":"Energy efficiency of computation is quickly becoming a key problem from the chip through the data center. This paper presents the first quantitative study of the potential energy efficiency of vector accelerators. We propose and study a vector accelerator architecture suitable for implementation in a 70 nm technology. The vector architecture has a high-bandwidth on-chip cache system coupled to 16 independent memory channels. We show that such an accelerator can achieve speedups of 10X or more on loop kernels in comparison to a quad-issue superscalar uniprocessor, while using less energy. We also introduce run-ahead lanes, a complexity and energy efficient means of tolerating variable latency from crossbar contention, cache bank conflicts, cache misses, and the memory system. Run-ahead lanes only synchronize on dependencies or when explicitly directed","PeriodicalId":333909,"journal":{"name":"ACM/IEEE SC 2006 Conference (SC'06)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM/IEEE SC 2006 Conference (SC'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1188455.1188537","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26

Abstract

Energy efficiency of computation is quickly becoming a key problem from the chip through the data center. This paper presents the first quantitative study of the potential energy efficiency of vector accelerators. We propose and study a vector accelerator architecture suitable for implementation in a 70 nm technology. The vector architecture has a high-bandwidth on-chip cache system coupled to 16 independent memory channels. We show that such an accelerator can achieve speedups of 10X or more on loop kernels in comparison to a quad-issue superscalar uniprocessor, while using less energy. We also introduce run-ahead lanes, a complexity and energy efficient means of tolerating variable latency from crossbar contention, cache bank conflicts, cache misses, and the memory system. Run-ahead lanes only synchronize on dependencies or when explicitly directed
矢量加速度的势能效率
从芯片到数据中心,计算的能源效率正迅速成为一个关键问题。本文首次对矢量加速器的潜在能量效率进行了定量研究。我们提出并研究了一种适合在70纳米技术中实现的矢量加速器架构。矢量架构有一个高带宽片上缓存系统耦合到16个独立的存储器通道。我们表明,与四问题标量单处理器相比,这样的加速器可以在循环内核上实现10倍或更多的速度,同时使用更少的能量。我们还介绍了超前通道,这是一种复杂且节能的方法,可以容忍来自交叉栏争用、缓存库冲突、缓存丢失和内存系统的可变延迟。超前通道仅在依赖项或明确指示时进行同步
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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