Novel MOS varactor device optimization and modeling for high-speed transceiver design in FinFET technology

Abstract

For the first time, an optimized MOS varactor device design and a new physical based varactor model for advanced FinFET process is presented for high speed analog applications. The varactor is optimized in process and cell design to achieve high tuning range and low jitter for PLL design. A new physical BSIMCMG based varactor model is developed with RF components to fully describe the 3D device in FinFET technology for high frequency applications. The power dependent varactor CV characteristics and modeling for accurate VCO simulation is described. The new varactor device and model has been validated in 32.75 GB/s high speed transceiver design in 16nm FinFET technology.