A CMOS rectifier with an extended high-efficiency region of operation

Abstract

A CMOS rectifier with a wide input signal range for radio-frequency identification (RFID) applications is presented. Using quasi-floating gate technique, a gate-biasing scheme is proposed to provide a relatively flat power conversion efficiency (PCE) curve for a wide input voltage (power) range. The proposed technique also enables an efficient operation for input voltage levels well below the standard threshold voltage of the MOS switching transistors. Appropriate bias voltages for different stages of the rectifier are generated through a chain of low-power bandgap reference generators which impose minimal power and area overhead. The proposed rectifier architecture is designed and laid out in a standard 0.13-μm CMOS technology. For a 2.4 GHz RF input frequency and 30 kΩ output load, post-layout simulation results of the circuit show that a maximum PCE of 66.7% is achieved for an input signal with an amplitude (power) of 0.45 V (-8 dBm). While a high PCE of 60% is achieved for input voltage (power) levels as low as 0.25 V (-15 dBm), PCE maintains above 60% for a wide input voltage (power) range from 0.25 V to 0.7 V (-15 dBm to -3 dBm).