A modified line expansion algorithm for device-level routing of analog integrated circuits

Abstract

CAD tools developed for routing analog circuits have to give special consideration for the quality of the routes developed, owing to the high sensitivity of these circuits to small changes in the layout geometry. Cost based path-finding algorithms that find globally optimal solutions are thus best suited for implementing routing in analog circuits. In this paper, we propose a modification to the line expansion algorithm used previously, that results in significant savings in time and memory consumed.