Investigation of Read Voltage Impact on Foundry BEOL RRAM for Core Integration

Abstract

In this paper, we investigated the influence of reading conditions on foundry BEOL RRAM characteristics for core transistor integration. The resistance states are statistically analyzed by varying read voltages from 0.05V to 0.4 V with a dedicated test flow to focus on cycle to cycle variation, nonlinearity and switching window. It indicates that optimization of reading voltage should be reviewed by leveraging switching window, read noise, and nonlinearity to obtain better read performance with a limited voltage swing range. This work aims to shed light on the co-impact of several common parameters in RRAM for advanced technology nodes.