A low-power DCT chip utilizing post-fabrication clock-timing adjustment with area reductions and adjustment speed enhancements

Abstract

A new post-fabrication clock-timing adjustment method using a genetic algorithm (GA) has been proposed to improve the performance of sub-100 nm LSIs. In the new method, we propose a new technique for implementing post-fabrication clock-timing adjustment, which is extremely effective in enhancing chip performance at almost negligible costs. The new technique comprises insertion-point prediction that specifies flip-flops to be adjusted in advance, and an improved GA technique for high-speed adjustment. We apply these techniques to an image-processing DCT (Discrete Cosine Transform) circuit that has low-power consumption characteristics, and developed a chip with 1,031 programmable delay circuits. The test chip circuit exhibits a more than 15% reduction in power consumption with an area increase of only 5%. The developed method is expected to realize adjustments within a few seconds.