A 1GS/s low-power low-kickback noise comparator in CMOS process

Abstract

A high speed comparator based on a high DC-gain folded-cascode amplifier is presented. Four switches rearrange the structure to speed up the comparison process and prevent kickback noise with a simple set of controlling signals. The circuit is a rail-to-rail folded-cascode amplifier during reset/evaluation period which transforms into two back-to-back inverters during the latch period to speed up the settling. The reset and the evaluation sequences are merged due to the special structure presented. This means that higher speed is achieved while reset time can be increased to erase the previous data completely. The comparator has been simulated in different conditions such as: temperature fluctuation, variations in process corners, power supply noise of 250mVp-p, clock skew of 80ps and applying the input signal in the most critical case. Results confirm that 1GS/s with 6-bit resolution is achieved for 1.6Vp-p and 10mV offset voltage while the power consumption is about 1mW. The most of the power supply noise is rejected while kickback noise and clock feed-through is reduced as well. Using the minimum size devices leads to a compact layout and die size of about 250(µm)2.