Linearity-enhanced Dual-power-mode CMOS RF Power Amplifier Design Using Post-distortion

Abstract

This paper presents the novel design of CMOS RF power amplifier (PA) with dual-power-mode operation and enhanced linearity. By the adoption of the proposed reconfigurable output network (for differential signal combining and impedance matching) and post-linearizing diode, the PA can be made to operate in either high-power (HP) or low-power (LP) mode with improved signal integrity. For verification, the proposed design is implemented using 0.35 µm CMOS process. Under continuous wave excitation, a power-added efficiency of 38.2% (31.3%) at 27.2 dBm (21.4 dBm) in HP (LP) operation is found. In addition, WCDMA test (carrier frequency of 2 GHz) results indicate that the proposed PA is capable of delivering average output power of 25.3 dBm (20.5 dBm) in HP (LP) mode, subject to 33 dBc ACLR specification.