Performance evaluation of optimized transistor networks built using independent-gate FinFET

Abstract

MOS planar technology has been used in fabrication of integrated circuits in the last decades. However, the short channel effects in the subthreshold operation region are becoming a critical restriction to the channel length reduction. With the use of FinFET devices, the scaling increases due the reduction of short channel effects. FinFET offers the possibility of independent gate controlling that can be efficiently exploited in logic reduction (network optimization), but with direct impact in the electrical performance of logic gates. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted transistor networks. Different logic gate implementations corresponding to the same Boolean function behavior are compared. The results demonstrate the existing tradeoff between these two parameters.