High level modifications of VHDL descriptions for on-line test or fault tolerance

Abstract

With the increasing probability of transient faults such as bit-flips due to SEUs and the increasing complexity of integrated circuits, the need for integrated mechanisms providing online error detection or fault tolerance is becoming a major concern, not only for classically critical applications, but also for circuits used in everyday life. This paper reports on a tool automating the implementation of some mechanisms by inserting modifications in high-level VHDL descriptions. The modifications are compatible with industrial design flows based on commercial synthesis and simulation tools. Implementation results are presented and compared with results previously obtained using a specific synthesis tool.