MPSoC FPGA-Based Radar Warning Receiver

Abstract

Identification of radar pulse signals is a crucial component in a radar warning receiver (RWR). Radar emitters transmit short radio frequency (RF) bursts, known as pulse trains, at specific operating parameters. Radar pulse train information is often stored in a list, known as a pulse descriptor word (PDW), and can be used to identify specific radar emitters. An RWR's primary function is to identify unknown radar signals and produce a PDW used to classify and sort signals for further processing, display, and countermeasures. This paper presents a multi-processor system-on-chip field-programable gate array (MPSoC FPGA)-based hardware implementation of an RWR system including deinterleaving algorithms and details the implementation environment, including hardware acceleration performance analysis.