B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, J. Meindl
{"title":"Optimal implementation of sea of leads (SoL) compliant interconnect technology","authors":"B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, J. Meindl","doi":"10.1109/IITC.2004.1345703","DOIUrl":null,"url":null,"abstract":"Compliant interconnects can enable wafer level packages with high I/O density, high reliability and better performances with low cost and small size. A fabrication process for SoL compliant interconnects has been optimized to achieve high yield and compatibility with standard back-end-of-line (BEOL) as well as flip-chip bonding processes. The optimized fabrication process further enables a reliable joining between the IC and SoL compliant interconnects to the next level of packaging without the use of an expensive underfilling process.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2004.1345703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Compliant interconnects can enable wafer level packages with high I/O density, high reliability and better performances with low cost and small size. A fabrication process for SoL compliant interconnects has been optimized to achieve high yield and compatibility with standard back-end-of-line (BEOL) as well as flip-chip bonding processes. The optimized fabrication process further enables a reliable joining between the IC and SoL compliant interconnects to the next level of packaging without the use of an expensive underfilling process.