Progress in submicron device technology

Abstract

Scaling of Metal Oxide Semiconductor (MOS) devices under submicron range experiences high device power dissipation due to large leakage current caused by Short Channel Effects (SCE). The use of high-K dielectric gate stack in MOS technology can solve these problems. The structure of the MOS device appears to be a vital issue below 22nm technology. The technologist devised FinFET, Tunnel FET (TFET), Carbon Nano Tube based TFET (T-CNFET), Nanowire-FET (NWFET) to remove the drawbacks of the existing technology. The various features of such devices have been discussed in this article.