A transmitter and receiver interface circuit including an equalizer and PFLL for 150 Mbit/s cable communication

J. Routama, K. Koli, P. Ruhanen, K. Halonen
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引用次数: 6

Abstract

This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal.
一种用于150mbit /s电缆通信的发送和接收接口电路,包括均衡器和PFLL
介绍了一种用于150mbit /s cmi编码数据传输的单片机收发接口电路。接收电路包括一个12db电缆均衡器来补偿非恒定电缆衰减和一个PFLL用于数据再生。发射器包括一个电缆驱动器,它为传输线提供稳定的IVpp信号幅度,以及一个锁相环来提取310mhz时钟信号。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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