A CMOS Envelope Detector for Low Power Wireless Receiver Applications

Abstract

Recent studies have shown that the power consumption of a wake-up receiver can be reduced by using an envelope detector as its first stage. Designing a low power envelope detector is challenging because of stringent requirements such as data rate, operating frequency, conversion gain and sensitivity. This paper describes the design of a 915 MHz envelope detector which uses a combination of active inductors and an input matching circuit to improve its conversion gain. The proposed design consumes 2 $\mu \mathrm{A}$ of bias current, achieves a 37.8 dB of conversion gain, a sensitivity of -60 dBm and a data rate of 200 kb/s in a 0.13 $\mu \mathrm{m}$ CMOS process.