The IP core design of PID controller based on SOPC

Abstract

This paper presents a method to design the PID controller IP core based on SOPC. The PID control algorithm, which is described by hardware description language on FPGA, is introducing to be the kernel of the PID controller IP Core in Quartus II 9.1 environment. Registers with parallel structure, specific Avalon bus interfaces and the drivers of the IP core are designed to achieve the transmission of the data between scheduling center and the IP core. The SOPC control system based on embedded Nios II processor with the core component PID controller IP core is designed to make temperature tests to the control object with features of first-order inertia and pure delay. The results show that, the step response of the system is of no overshoot, zero steady-state error, short rise time, and good anti-interference effect. The implementation of this design is reusable and convenient for being invoked by intelligent PID control system.