VHDL intermediate form standardization: process, issues and status

Abstract

The activity involved in developing a standard intermediate form for the IEEE VHSIC hardware description language (VHDL) is presented. The purpose of this intermediate form is to provide a common computer-aided design (CAD) tool interface for systems described by the VHDL. The IEEE group responsible for developing the standard is introduced, followed by a description of the four-step process used by the group in developing the standard. The current status of the effort is discussed as well as the future plans for converging on the goal of developing a standard intermediate form for VHDL.<>