R. Sarmiento, C. Pulido, F. Tobajas, V. Armas, R. Esper-Chaín, J. López, J. Montiel-Nelson, A. Núñez
{"title":"A 600 MHz 2D-DCT processor for MPEG applications","authors":"R. Sarmiento, C. Pulido, F. Tobajas, V. Armas, R. Esper-Chaín, J. López, J. Montiel-Nelson, A. Núñez","doi":"10.1109/ACSSC.1997.679159","DOIUrl":null,"url":null,"abstract":"In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.","PeriodicalId":240431,"journal":{"name":"Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1997.679159","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.