A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 /spl mu/m CMOS with 99 dB SFDR

Abstract

A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.