Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory

S. Dutta, H. Ye, W. Chakraborty, Y. Luo, M. Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, S. Datta
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引用次数: 38

Abstract

We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf0.5Zr0.5O2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget (<4000C) processing to integrate HZO with 1% Tungsten (W)-doped amorphous In2O3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2PR, of 40μC/cm2 reliable with switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >108 cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3× higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.
用于加速内存中计算的高耐用多比特铁电场效应管单片三维集成
我们首次展示了后端线(BEOL)兼容的Hf0.5Zr0.5O2 (HZO)铁电场效应管(FeFET)与前端线(FEOL)高k/金属栅极(HKMG) Si-NMOS的单片3D (M3D)集成。我们使用低热预算(108循环)。我们进一步展示了一个2比特/细胞的突触重量细胞,其电导状态分离良好。使用VGG-8模型对CIFAR-10图像数据集进行推理的内存中计算(CIM)加速器系统级分析表明,22nm BEOL FeFET的能效比7nm SRAM高3倍,同时由于M3D架构实现了面积折叠,占用了更小的存储阵列面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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