Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors

Abstract

In this paper, a novel self-recoverable SRAM cell, namely SRS14T cell, is proposed in 22nm CMOS technology. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors, the cell provides the following advantages: (1) It can self-recover from single node upsets (SNUs) and partial double-node upsets (DNUs); (2) it can reduce access time and power consumption. Simulation results validate the robustness of the proposed SRS14T cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SRS14T cell can reduce read access time, write access time and power dissipation by 56.64%, 21.03% and 19.26% on average, respectively, at the cost of moderate silicon area.