Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters

Abstract

Run-time power gating for aggressive leakage reduction has brought into focus the cost of mode transition overheads due to frequent switching between sleep and active modes of circuit operation. In order to design circuits for effective power gating, logic circuits must be characterized for overheads they present during mode transitions. In this paper, we describe a method to determine steady-state virtual-supply voltage in active mode and hence present a model for virtual supply voltage in terms of basic circuit parameters. Further, we derive expressions for estimation of two mode transition overheads: wakeup time and wakeup energy for a power-gated logic cluster using the proposed model. Finally we demonstrate its application to four ISCAS benchmark circuits while also analyzing the accuracy of approximations used in the model.