A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology

Abstract

At lower technology, the static power dissipation and stability of conventional six transistors static random access memory (SRAM) cell poses a major issue. To address this issue, a novel eleven transistor (11T) SRAM cell for improving read stability and reducing the static power dissipation is proposed in this work. In the proposed 11T SRAM cell, the storing node isolates from the read bit line using separate read port while sleep transistor methodology is explored for power saving. With this the read static noise margin (RSNM) value of proposed design is enhanced by 6x, 2.3x, 2.7x and 1.3x when compared with basic 6T SRAM cell, 11T ST2 SRAM cell, 11T ST1 SRAM cell, ST11T SRAM cell respectively. The write stability is also enhanced by 1.6x over basic 6T SRAM cell, 1.14x over 11T SRAM and penalty of 1.17x when compared with other 11T SRAM cell. Further, using the sleep transistor methodology the static power consumption of the proposed design has been reduced by 4.6x when compared with basic 6T SRAM cell. The proposed 11T SRAM cell has been verified in 40nm CMOS technology node using cadence virtuoso tool.