Adaptive Clock and Data Recovery for Asymmetric Triangular Frequency Modulation Profile

Abstract

Clock and Data Recovery (CDR) is an important block in Serializer/Deserializer (SerDes) systems used to recover the clock from the bitstream. With high data rates, the effect of Electromagnetic Interference (EMI) is increased. Several spreading spectrum profiles are able to reduce the effect of EMI. Asymmetric spreading spectrum profile is one of the types that can be implemented easily and can make a significant reduction on EMI. The challenge in CDR design is increased with asymmetric spreading profiles as the slew-rate is high with respect to the other profiles. Many researches provided several architectures for adaptive CDR with symmetric spreading profiles. In this research, a new architecture is proposed to detect the large phase error to reach suitable CDR controller parameters needed to recover the clock with high slew-rate profiles. The proposed architecture is able to get locking with the incoming data in short-time even with an initial large difference between transmitter and receiver clock frequency and at the same time achieve minimum jitter. A white Gaussian noise with 30 dB Signal to Noise Ratio (SNR) is used on a channel model to simulate the actual behavior on SIMULINK. Also, a search algorithm is proposed to find the best CDR settings in the proposed architecture. Results obtained from MATLAB shows the efficiency of the proposed architecture to track the data with largest slew-rate using sudden step change on transmitter clock frequency.