A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

Abstract

A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.