Exploring Resource-Aware Deep Neural Network Accelerator and Architecture Design

Baoting Li, Longjun Liu, Jiahua Liang, Hongbin Sun, Li Geng, Nanning Zheng
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Abstract

Due to the ever-increasing number of neural networks(NNs) connections and parameters, computation on neural networks is becoming both power hankering and memory intensive. In this paper, we propose a sparse neural networks accelerator to improve memory resource utilization and improve power efficiency. In contrast to prior works, we introduce a highly integrated software and hardware co-design technique that combines resource-aware software compression algorithms and specialized hardware inference engine in the accelerator. Compared with other designs, our design can compress parameters by 90× and substantially improve storage resource utilization, performance (6.9×) and power (1.2×) for NN accelerators.
探索资源感知深度神经网络加速器与体系结构设计
由于神经网络连接和参数的不断增加,神经网络的计算变得越来越耗能和内存密集型。在本文中,我们提出了一个稀疏神经网络加速器,以提高内存资源利用率和提高功率效率。与先前的工作相比,我们引入了一种高度集成的软件和硬件协同设计技术,该技术将资源感知软件压缩算法和专用硬件推理引擎结合在加速器中。与其他设计相比,我们的设计可以将参数压缩90倍,大大提高了NN加速器的存储资源利用率、性能(6.9倍)和功耗(1.2倍)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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