A Dynamically Configurable Network for Software-Defined Hardware

Abstract

This paper describes an on-die network architecture targeted for Software-Defined Hardware (SDH). Key performance goals are near ASIC-level performance over a wide range of communication patterns, dynamically configured for operation on tile arrays with O(104) tiles and defect densities in excess of 10%. We describe a network architecture based on two recent Intel circuit studies, and present simulator results that demonstrate extremes for configurability, scale-invariant place & route and resilience to defect