A Formal Modelling Language for Digital Electronic Systems Design

Abstract

Today’s electronic digital systems are becoming more complicated, thus designing such systems requires a higher level of abstraction and design automation. To address this concern, this paper proposes a new formal Domain specific Modelling Language (DSML) called DSysML for DES modelling. The proposed DSML extends the Block Definition D iagram (BDD) and Internal Block Diagram (IBD) SysML diagrams to include electronic concepts, and employs a familiar graphical notation from the DES domain. This enables modelling DES systems at a high–level of abstraction. Due to its formal semantics, DSysML makes it possible to validate DES designs through simulation and formal verification. This letter is defined by a functional language specification t hat w as a utomatically g enerated. T he proposed DSML is illustrated through a case study of an Arithmetic and Logic Unit (ALU).