Design of CMOS low noise amplifier for 1.57GHz

Abstract

This paper is enunciated a LNA with high gain and minimum noise performance for Global Positioning System (GPS) application. The CMOS Low Noise amplifier implementation is designed and simulated via cadence using UMC 90 nm library. The topology is single ended LNAs designed which uses cascaded transistor for isolation; the common source transistor is driven by common gate transistor. To have objective for good voltage gain with minimum noise figure, cascoding input matching is done using source degeneration technique. Transistors are operated in sub threshold region. At 1.57 GHz frequency, parameters like power gain, input matching, output matching, isolation, stability are examined by S-parameters. The voltage gain of LNA is 31 dB. The noise figure is 0.533 dB, 1dB compression point is -16.95 dBm and IIP3 is 2.91 dBm. The LNA is having power consumption as 8.7 mW for 1.5 V supply.