A novel current-mode Winner-Take-All topology

Abstract

In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13µm CMOS process and characterized in terms of resolution, resolution speed, supply voltage, compactness and power consumption. The novel WTA shows the highest resolution speed and the best trade-off between performance parameters.