A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Abstract

A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.