CORDIC implementation with parameterizable ASIC/SoC flow

Abstract

A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power numbers at both technology nodes are reported for the CORDIC design. The contribution of the paper includes both the actual design and the design flow.