An extension of RSA_512 to RSA_1024 core under hardware platform based on montgomery powering

Abstract

A hardware implementation of RSA encryption based on Montgomery algorithm with modular multiplication and systolic array architecture is presented. In this paper, we present an extension of RSA core from 512 key lengths to 1024 key length under hardware platform. The design uses two block multipliers as the main functional unit and Block-RAM as storage unit for the operands. To extend the core from 512 bits to 1024 bits, the design keeps the same IP-Core architecture, it will only adjust the radix used in the multipliers, and number of words to meet the system requirements such as available resources, precision and timing constraints. The architecture, based on the Montgomery modular multiplication algorithm, utilizes a pipelining technique that allows concurrent operation of hardwired multipliers.