A High Speed Clock Receiver for DAC with Cross point and Duty Cycle Adjustable Capability

Abstract

This paper introduces a kind of high speed clock receiver for DAC with cross point and duty cycle adjustable capability. In this paper the circuit realizes cross point and duty cycle adjustable function by changing the node common-mode voltage in the signal path with different ways. It can obtain the satisfying cross point and duty cycle through the negative feedback loop. In the post simulation the cross point of the output clock signal meets the design requirements, and the duty cycle is adjusted from 45% to 50.09%. So the error from the target value is less than 0.1%.