Modeling the Probabilities of Failures of 22 nm CMOS Logic Cells

Abstract

In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes, the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.